This invention relates to Magnetoresistive Random Access Memories (MRAMs) and other memories where the memory bit has at least two distinct resistance states, and more particularly to sense amplifier circuits for such memories.
Non-volatile memory devices, such as FLASH memories, are extremely important components in electronic systems. FLASH is a major non-volatile memory device in use today. Disadvantages of FLASH memory include high voltage requirements and slow program and erase times. Also, FLASH memory has a poor write endurance of 104-106 cycles before memory failure. In addition, to maintain reasonable data retention, the scaling of the gate oxide is restricted by the tunneling barrier seen by the electrons. Hence, FLASH memory is limited in the dimensions to which it can be scaled.
To overcome these shortcomings, other types of nonvolatile memories are being evaluated. One such device is magnetoresistive RAM (hereinafter referred to as xe2x80x9cMRAMxe2x80x9d). To be commercially practical, however, MRAM must have comparable memory density to current memory technologies, be scalable for future generations, operate at low voltages, have low power consumption, and have competitive read/write speeds.
MRAM bit cells store data by varying the resistance of a magnetic tunnel junction (MTJ) between low (R) and high (R+dR) states. For most memories, the state of the memory cell is determined by comparing the memory cell to a reference, often a midpoint value. Accordingly, for MRAM, the reference is developed as a midpoint reference, an average of high and low states, to provide a mechanism to determine the stored value in a cell. In U.S. Pat. No. 6,236,611 entitled xe2x80x9cPeak Program Current Reduction Apparatus and Methodxe2x80x9d by Naji a solution is offered wherein a combination of four reference bits, two high and two low, provide a midpoint reference. However, MTJ resistances are not linear. The series and parallel combination used by Naji does not produce a true midpoint reference. There is an asymmetry between the difference from the high value to the reference and the difference from the reference to the low value. Additionally, symmetry in bit line capacitance is desired and is more problematic with references using multiple resistances. In U.S. Pat. No. 6,269,040 by Reohr et al. entitled xe2x80x9cInterconnection Network For Connecting Memory Cells to Sense Amplifiersxe2x80x9d, a memory circuit is disclosed in which a midpoint reference is obtained by averaging memory reference cells, one high and one low. The midpoint reference shares signals between references from adjacent arrays via an interconnect network that is almost but not fully balanced. In the Reohr et al. memory, two sense amplifiers are required to perform the averaging. Thus, a need remains for a sensing circuit using a midpoint reference that requires a minimum of area, provides a true nearby midpoint reference, and maintains symmetry in the circuit path for balanced loading including parasitic capacitances and resistances.